(1) Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to a method for fabricating an array of dynamic random access memory (DRAM) cells with cactus-shaped stacked capacitors to increase the capacitance while maintaining a high density of memory cells.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits (devices) are extensively used in the electronics industry, and more particularly in the computer industry for storing data in binary form (1 and 0) as charge on a storage capacitor. These DRAM devices are made on semiconductor substrates (or wafers) and then the substrates are diced to form the individual DRAM circuits (or DRAM chips). Each DRAM circuit (chip) consists in part of an array of individual DRAM storage cells that store binary data (bits) as electrical charge on a storage capacitor. Further, the information is stored and retrieved from the storage capacitor by means of switching on or off a single access transistor (via word lines) in each memory cell using peripheral address circuits, while the charge is stored on the capacitor or sensed via bit lines and by read/write circuits formed on the periphery of the DRAM chip.
The access transistor for the DRAM device is usually a field effect transistor (FET), and the single capacitor in each cell is either formed in the semiconductor substrate as a trench capacitor, or built over the FET in the cell area as a stacked capacitor. To maintain a reasonable DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip. Unfortunately, as the cell size decreases, it becomes increasing more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. The reduced charge also requires more frequent refresh cycles that periodically restore the charge on these volatile storage cells. This increase in refresh cycles further reduces the performance (speed) of the DRAM circuit.
Since the capacitor area is limited to the cell size in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the lateral area that the capacitor occupies on the substrate surface. In recent years the method of choice is to build stacked capacitors over the access transistors within each cell area, rather than forming trench capacitors which need to be etched to increasing depths in the substrate to maintain the necessary capacitance. The stacked capacitors also provide increased latitude in capacitor design and processing while reducing cell area. More specifically, the stacked capacitors can be extended in the vertical direction (third dimension) to increase the stacked capacitor area, and therefore to increase the capacitance.
Numerous methods of making DRAM circuits using stacked capacitors have been reported in the literature. One method of making fork-shaped stacked capacitors using sidewall spacers is described by Tseng in U.S. Pat. No. 5,643,819. Another approach for making multiple-walled capacitors using sidewall spacers as an etch mask for etching the multi-walled structure for the bottom electrodes is taught by Sim et al. in U.S. Pat. No. 5,399,518. Still another approach is taught by Liaw et al. in U.S. Pat. No. 5,543,345, in which sidewall spacers are used as an etch mask to form a crown-shaped capacitor. Another method for making stacked capacitors having E-shaped capacitor bottom electrodes is taught by Tseng in U.S. Pat. No. 5,604,146.
Although there has been considerable work done to increase the capacitance area on these miniature stacked capacitors, it is still desirable to further improve on these capacitors while maintaining a simple process using self-aligning techniques to minimize the number of masking steps.